1. Field of the Invention
The present invention relates to an imaging device with reduced occurrence of flicker.
2. Description of the Related Art
Various studies have been made for an imaging device, particularly for a method of reading signals therein. For example, Japanese Laid-open Patent Publication 2000-165754 discloses a signal reading method for the purpose of increasing dynamic range. FIG. 1 and FIG. 2 correspond to FIG. 12 and FIG. 13 of the Patent Publication, respectively, which are a diagram of a pixel circuit of the fourth example described therein, and a timing chart showing the operation of the pixel circuit. The purpose of this signal reading method is not to reduce the occurrence of flicker, but to increase dynamic range as described above. However, since this method can be applied to reduce the occurrence of flicker under the illumination of a fluorescent lamp, this method will be described below as an example of a prior art.
FIG. 1 is a circuit diagram of a pixel circuit in a CMOS (Complementary Metal Oxide Semiconductor) image sensor applied to the conventional imaging device which has two transfer switches, i.e. a first transfer switch (transfer transistor) MTX1 and a second transfer switch (transfer transistor) MTX2, for one pixel. The pixel circuit has a floating diffusion capacitance CFD1 between the first transfer switch MTX1 and the second transfer switch MTX2 as well as a floating diffusion capacitance CFD2 between the second transfer switch MTX2 and a source-follower amplifying transistor MSF. In FIG. 1, reference symbols PD, MRES and MSEL designate a photodiode, a reset switch (reset transistor) and a selection switch (selection transistor), respectively.
This pixel circuit is designed to be able to switch a capacitance to be connected to the gate of the amplifying transistor MSF, between either a parallel connection of the capacitances CFD1, CFD2 or only the capacitance CFD2, under the control of a signal of a gate voltage φTX2 applied to the transfer switch MTX2 as shown in FIG. 2 which is a timing chart showing an operation of the conventional pixel circuit. In FIG. 1 and FIG. 2, other reference symbols φRES, φTX1 and φSEL designate gate voltages of the reset switch MRES, transfer switch MTX1 and selection switch MSEL, respectively, while reference symbol OUT designates an output voltage (output signal) from the pixel circuit. In FIG. 2, furthermore, other reference symbols R(P), R(C), RR(C1, C2), RR(C2), CT, RS(C1, C2) and RS(C2) designate a reset point of the pixel (photodiode) at which the photodiode PD starts charge accumulation, a reset period of the pixel, a reset level reading period of the capacitances CFD1+CFD2, a reset level reading period of the capacitance CFD2, a charge transfer period, a signal level reading period of the capacitances CFD1+CFD2 and a signal level reading period of the capacitance CFD2, respectively.
Photogenerated carriers accumulated in the photodiode PD are divided and transferred to the capacitances CFD1, CFD2, because the gate voltage φTX1 of the first transfer switch MTX1 is brought to a high level when the gate voltage φTX2 of the second transfer switch MTX2 is at a high level. Thereafter, the gate voltage φTX1 of the first transfer switch MTX1 is brought to a low level so as to read a signal based on photogenerated carriers stored in the capacitances CFD1, CFD2. Assuming that the voltage applied at this time to the gate of the amplifying transistor MSF is VFD2, and the amount of charge of the photogenerated carriers is QPD, the voltage VFD2 can be expressed by:VFD2=QPD/(CFD1+CFD2)where CFD1, and CFD2 are values of the capacitances CFD1, CFD2.
Next, charge having been stored in the capacitance CFD1 is transferred to the capacitance CFD2, and thereafter the gate voltage φTX2 of the second transfer switch MTX2 is brought to a low level, so as to read a signal based on the photogenerated carriers stored in the capacitance CFD2. A voltage VFD2H applied at this time to the gate of the amplifying transistor MSF can be expressed by:VFD2H=QPD/CFD2.A comparison between the voltages VFD2 and VFD2H indicates that the former VFD2 is lower than the latter VFD2H because of the capacitance value CFD1 in the denominator, meaning that the former VFD2 causes a lower sensitivity.
As will be described below, the occurrence of flicker can be reduced by selectively using the two voltages VFD2, VFD2H depending on required sensitivity. In normal brightness mode where an image received by the imaging device (specifically, photodiode) is in a normal brightness range, flicker is unlikely to occur. In this normal brightness mode, the imaging device is likely to be able to normally operate (e.g. produce an accurate or high fidelity image) even if the photodiode has a normal or long charge accumulation time (e.g. longer than a half period of a commercial AC power supply) with a normal or high pixel sensitivity. Thus, in the normal brightness mode, the imaging device uses a signal based on the voltage VFD2H (higher than the voltage VFD2), which is applied to the gate of the amplifying transistor MSF with only the capacitance CFD2 storing charge, so as to cause the pixel sensitivity to stay normal or high.
On the other hand, in high brightness mode where an image received by the imaging device is in a high brightness range, flicker is likely to occur. In this high brightness mode, the imaging device is unlikely to be able to normally operate if the photodiode has a normal or long charge accumulation time (e.g. longer than a half period of a commercial AC power supply) with a normal or high pixel sensitivity. Thus, in the high brightness mode, the imaging device uses a signal based on the voltage VFD2 (lower than the voltage VFD2H) applied to the gate of the amplifying transistor MSF with both capacitances CFD1, CFD2 dividedly storing charge, so as to cause a lower pixel sensitivity, thereby achieving reduction of occurrence of flicker even with the normal or long charge accumulation time.
However, the imaging device according to the Japanese Laid-open Patent Publication 2000-165754 as described above requires two capacitances CFD1, CFD2 together with two transfer switches MTX1, MTX2 for one pixel. This is a problem because it causes the circuit structure to be complicated, thereby increasing the manufacturing cost of the imaging device.